/* NAU - Team Wulfsberg
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The Project

In this project, we were tasked with creating a receiver that incorporated a FPGA. This receiver was meant to take information coded in a wave, using a modulation technique of our choosing, and retrieve it. The only stipulation for this was that it had to incorporate a FPGA, coded in our choice of Verilog or VHDL, and had to take care of the demodulation aspects of retrieving a signal. We were given several liberties about how exactly how to approach the project, most of which can be found on the specifications page.
In the end, we chose to use the Altera Cyclone II FPGA chip, and coded the FPGA program in both VHDL and Verilog, but primarily Verilog. Our receiver itself uses a 8-PAM (pulse amplitude modulation) modulation technique because of its high information density and the familiarity it had with the members of our group. Our input test values is a stream of numbers generated by Matlab.

To the left, you will find links to various aspects of our project, from our design process to the software and hardware we used for this project. Also, keep in mind that this web site only contains a brief summary of our project. For a more complete overview, please download our project report.

Design Overview

Below is a picture showing overall design of our product, followed by a list giving more information about each section. Again, more information can be found in our final results paper.

  1. Analog Section (not pictured)
    • Accept the incoming signal and prepare the signal for use in the FPGA
    • Section Status: Removed from our design in part 2 of the design phase, in favor of generating the incoming signal with Matlab
  2. ADC (Analog to Digital Converter, not pictured)
    • Convert the signal from the analog domain to the digital domain
    • Section Status: Removed from our design in part 2 of the design phase, in favor of generating the incoming signal with Matlab
  3. Down conversion
    • Code Language: Verilog
    • Used to down convert the signal for easier use in the FPGA
    • Section Status: Complete (03/07/10)
  4. Low Pass Filter
    • Code Language: Verilog
    • Used to cut of the unnecessary components that resulted from the down conversion.
    • Section Status: Complete (02/28/10)
  5. Channel Selection
    • Code Language: VHDL
    • Used to enable the user to select whichever channel they wish
    • Section Status: Complete (Base Code 02/18/10; User Interface 04/07/10)
  6. Demodulation
    • Code Language: Verilog
    • Used to demodulate the signal using the 8-PAM modulation
    • Section Status: Incomplete
  7. Audio CODEC (Coder/Decoder)
    • Code Language: Undecided
    • Our demodulated signal will be sent to the CODEC for output to the user. The CODEC also includes a digital to analog converter.
    • Section Status: Incomplete