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Design Plan - Test Phase
April 2010 -> May 2010
Following the completion of our code, we needed to test it. As with the code creation, we split this task up among the different group members to lighten and simplify the testing process.
The majority of the testing was done by running simulations on our code using the Mentor Graphics Altera-ModelSim program. During our testing phase, it was discovered that the FPGA chip we had selected was not powerful enough to run the entire program. Since we had no other FPGA chip available to us, we attempted to optimize the code to the best of our ability. While optimizing the code did significantly help, it still wasn't enough to allow the FPGA chip to run the entire program at once. Our only other choice was to cut out some of the calculations that the FPGA needed to do. This, however, would cause our receiver to not completely reach the product specifications that were required by the customer. In the end, we were not able to run the entire program on the FPGA, as we simply ran out of time and resources.
Milestones Reached
- Successful test of both the low pass filter, and the channel selection code independently
Tools Used
- Mentor Graphics ModelSim
- Altera Quartus II
- Altera DE2 Prototype board
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