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Design Plan - Implementation Phase
February 2010 -> April 2010
Starting in February, we began the program needed for our project. As the product required a very complex program, we elected to split the program up into smaller programs, and then later link the separate programs together to create single, complete program. This was possible thanks to the flexibility of both the Verilog and VHDL languages, as well as the ability for our design software to combine and synthesize two different languages into a single programmable file. Each group member would take one of these smaller programs and code the program independently of the other sections. This tactic actually proved quite beneficial to us, as it was significantly easier to test and locate errors on each section independently, rather than the entire program as a whole.
Milestones Reached
- Low Pass Filter code completed (mid-February)
- Channel Selection code completed (late-February)
- Demodulation code completed (early-March)
- User interface for channel selection completed (early-April)
Tools Used
- Altera Quartus II
- Mentor Graphics Altera-ModelSim
- Matlab
- Various basic text editors (Notepad++, VIM, etc.)
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