The following sections cover the six major categories of requirements and specifications, including physical requirements of the design and the FPGA, and software requirements of working with the FPGA during development and during use.
Mechanical requirements for this project are extremely loose considering the prototypical nature of the project. This is especially present in these early phases before sensors or actuators are added. We will eventually want the ability to expand the system by adding these in, which will most likely involve physically adding components to the system. The mechanical/physical characteristics should be reasonable for a typical FPGA-based embedded systems project. The values that follow are estimated to be reasonable upper bounds for the basic physical traits.
| Specification | Quantity | Comments |
|---|---|---|
| Weight | < 8 Lbs | N/A |
| Area | < 95 in2 | N/A |
The electrical specifications of this project are minimal. Because the project is designed and implemented on an FPGA, we will be dealing with any electrical constraints on a small scale. FPGAs are powered by USB, a small wall adapter, or a battery pack, which are the only electrical needs. When the team begins to add sensors to the FPGA, we will need to pay attention to the voltage requirements of the sensors to ensure the board supplies the proper levels. These are the electrical constraints. The project could be more flexible if the device is capable of supporting a range of voltages such as 1.8V, 3.3V, 5V, or up to 12V.
| Specification | Quantity | Comments |
|---|---|---|
| Power | 1.8V to 12V | Exact Value will be determined by final FPGA selection |
This project will have a low environmental impact at the user level. However, the design will contain environmental variables that impact the functionality of the device. The device implementation must be kept within the constraints of the FPGA that is chosen for the project, such as operating temperature. The project code must be designed to operate within the timing constraints provided by the FPGA. The design must also match the timing of the peripherals and sensors that will be used to ensure a fluid transfer of data throughout the device.
| Specification | Quantity | Comments |
|---|---|---|
| Temperature | -40℃ to 80℃ | The operating temperature for the devices to function. |
| Timing Delay | ≥ 0 timing delay | This value is determined by taking the clock delay – the datapath delay |
| Timing requirements | Synchronized clocks | The design must use a universal or a synchronized clock source throughout. |
The documentation for this project is related to the top-level design. Since the project is based on an FPGA board, we will be dealing with the needs and give corresponding documentation on the part of the design which will be directly accessed by the users. There will also be inward facing documentation that will be used by the team to track the project development.
| Specification | Comments |
|---|---|
| User's Manual | The operator’s manual might contain the following sections:
|
| Code | Source code (and source code documentation) will be protected and managed through a git repository. |
The project FPGA implementation will be coded in the SystemVerilog HDL programming language. The language is expansive and flexible and will allow for a functional design to be created within the project time constraints. Each FPGA comes with a design suite to allow easier programming and communication with the FPGA. Our SystemVerilog code will be constrained by the language implementation of whichever software suite is chosen for development. If time allows, a simple method of interaction with the design through a custom C compiler will be implemented.
| Specification | Quantity | Comments |
|---|---|---|
| Software | FPGA design suite | The integrated software environment for the selected FPGA board. |
| Design Language | SystemVerilog | The language in which the core elements of the design are written, constrained by the FPGA design suite. |
| User Language | C | Will implement a C compiler |
The remaining general requirements for this project are related to the FPGA selection. The client wants the FPGA to be flash-based instead of SRAM based because the bootup sequence is more secure and reliable. If we are unable to find a suitable flash-based FPGA, the project will use an SRAM-based board. The HDL design of the project will require significant FPGA fabric resources to support the multiple processors and the sensor interfaces. The development board used must also contain enough I/O ports to handle the sensors we use. There are no constraints for the FPGA.
| Specification | Quantity | Comments |
|---|---|---|
| FPGA style | Flash or SRAM based | Depends on final FPGA selection |
| FPGA resources | 12000+ Tiles / 600,000+ Gates | FPGAs measure resources differently. |
| FPGA I/O | Minimum I/O for one sensor, Ideally enough for as many sensors as we implement | Final count will depend on number and types of sensors chosen for the project |