Large scale DRAM Array Model
Abstract
Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that stores single bits in a capacitor within an integrated circuit. This form of memory is often used in everyday electronics, such as computers and smartphones. Micron Technology is one of the leading manufacturers of DRAM in the United States. Currently, Micron recruiters have no way of simulating their product’s functionality to consumers and potential engineers. Our client Micron Technology, requested an interactive, functional, large scale DRAM array model to emulate the operations of DRAM such as writing to, reading from, and refreshing the memory array, through a user interface. The array is comprised of sixty-four cells, denoting that sixty-four bits of memory can be stored on the array at once for a short period of time. Via grid connected push buttons, the user will be able to interact with the array by selecting a cell to perform a write action upon.. An LED on each cell will indicate successful bit storage by brightening or dimming based off if a “1” or “0” was stored. The DRAM model will be used by Micron recruiters to simulate functionality, design, and composition of the sixty-four cell array. This model provides Micron with an interactive solution for explaining basic DRAM operations of write, read, and refresh to consumers and prospective DRAM engineers.
Goal of The Project
In the field of memory and memory applications, Micron’s capstone group will design and build a large scale Dynamic Random Access Memory (DRAM) model with multiple electrical components, such as capacitors, Metal-Oxide Semiconductor Field Effect Transistors (MOSFETs), LEDs, and a microcontroller or FPGA for under $100.
Documentaion Regarding The Model
As a final requirement of the project, a User Manual was created on how to operate and maintain the DRAM model. The manual also provides insight into why this project was undertaken, how it was designed and completed, and what future work could be done to improve the model. Our client, Daniel Eichenberger, is a Recruiter for Micron Technology, who’s most profitable product are semiconductor memory devices based off the structure of DRAM. So, he asked the team to design, test, and build a large scale model of a DRAM Array which simulates the three basic functions of DRAM; writing to, reading from, and refreshing the memory array. The team accomplished this task by designing a 64-bit array, using the basic m-bit cell structure to store memory and external inputs such as push buttons emulating digitline and wordline control pulses. In Fall of 2018, Daniel plans to come back to recruit at NAU’s Semi-Annual Career Fair and use the model as a teaching device for engineering students interested in pursuing a career with Micron, showing them what they may work as a Micron employee. Please refer to the “Uploaded Documents” tab to view the complete User Manual.