Project Description


Problem Statement

To design and implement a Reconfigurable Computing Card (RCC) that will support the NAU Electrical Engineering Program, attempting to teach valuable skills applicable to the job market that aren't taught in the classroom.  The project will not directly benefit SEAKR Engineering.

System Diagram

The Reconfigurable Computing Card (RCC) shall have the following

Altera Cyclone III FPGA (Field Programmable Gate Array): The brain of the RCC.  It controls and  reads the inputs and outputs and decides what needs to be done with them

JTAG: Interface for loading the configuration PROM, which in turn programs the FPGA at startup.

LCD Display:  Receives output data from FPGA, provides visual representation of program using text and / or graphics.

Header: Inputs and outputs that allows us to connect other components to the RCC.

LED Bank:  Receives output data from FPGA, provides a visual representation of the Traffic Light Controller program operation.  Also used for debugging.

Reset: Resets all of the components to a known state.  If an error occurs, allows us to recover from it.

Power: Powers all of the components

System Diagram

Requirements/Specifications

Mechanical

                Mechanical requirements dictate physical constraints for the device, and physical effects that the device may be subjected to. The product must adhere to a certain form factor, and as such, board real estate is limited and precious. Physically speaking, the board must have a way to interface with outside sources for inputting and outputting data.

Specifications:

Fit 3U Form Factor (4” x 6” PCB)

20 Pin Header for interfacing bench test equipment

PC Based interconnect for loading VHDL images

ESD sensitive equipment

Plastic Quad Flat Pack

Jumper pin determines which FPGA image will be loaded when powered.


Electrical

                Electrical requirements pertain to powering the device, and the various voltage levels it calls for. The board will be provided a specific, uniform DC voltage, and must down-convert this voltage to drive various internal components. Some components have relatively small tolerances, so the supplied voltages must be controlled with precision.

Specifications:

Power consumption of the end product should not exceed 10 watts

10 VDC bench power will be provided to power the Reconfigurable Computing Card (RCC)

FPGA constraints require precise control of voltages.

Derating of components

All single ended signal impedances must be matched to 50 Ω

All differential signal impedances must be matched to 100 Ω


Environment

                When designing a device, it is incredibly important to understand the environment the device is intended to operate in. Environmental factors include temperature, humidity, static electricity, etcetera, and influence what components are used in the final design.

Specifications:

Room temperature

RoHS compliance of materials


Testing

                It is hopeful, although unlikely that everything will behave exactly as expected on the first iteration of the design. Therefore, it is important to have a thorough and consistent testing algorithm to completely address potential shortcomings of the design.

Specifications:

Power and ground continuity test of board after fabrication

VHDL implemention of images will be simulated with software applications.

 
Documentation

                Documentation should be an ongoing process during the design, and should subsequently describe its various phases. The documentation will also be a reference to the end user, providing insight on proper usage of the device and how the design was implemented on the software side.

Specifications:

Operator’s Manual

User’s Guide

HDL Source Code


General

                General requirements encompass constraints that do not otherwise fit into the aforementioned requirement categories. These requirements describe general project criteria pertinent to successful operation.

Specifications:

SEAKR Engineering, Inc. will be responsible for fabrication of board over NAU winter break

Reset must reset all components to a known state

PROM will store three unique FPGA images