Hardware Design for Post-Quantum Cryptography Polynomial Multiplier

Project Overview

Our project focuses on building a hardware design to optimize polynomial multiplication for post-quantum cryptography, specifically targeting the CRYSTALS-Kyber algorithm. This design will be implemented onto an FPGA board for use.

Current encryption methods don't provide enough protection to prevent brute force attacks from future quantum computers. Within the next few decades, it is likely that the development of quantum computers will progress far enough to pose a serious risk. Therefore, building tools to support post-quantum cryptography is incredibly valuable in protecting digital security.

Goals

• Understand NTT multiplier, verify existing NTT multiplier on software (Python/C/C++/Julia).
• Complete Verilog/SystemVerilog code to perform NTT polynomial multiplication on Xilinx Vivado.
• Complete parallel NTT multiplier on Xilinx Vivado and/or propose solutions to improve NTT multiplier.

NAU Engineering FEST - Fall 2024