Phase-Locked Loop Senior Design Project Team C Northern Arizona University Sponsored by Communications Technology Center Motorola Don Taylor and Gene Heimbecher Team C Members
			From left to right: Michael Gallman, Aaron Cleaver, Michelle East, and Ron Green

Motorola is participating in the electrical engineering Capstone Senior Design Project. Sponsor contacts are Don Taylor and Gene Heimbecher at Motorola Communications Technology Center. This project is a two-semester process. Fall semester entails creating a proposal for acceptance based on Motorolas criteria. Spring semester involves implementing the accepted proposal. Northern Arizona University’s Team C, is comprised of Aaron Cleaver, Michelle East, Ron Green and Michael Gallman.

Overall Project 

Team C has researched PLL theory, is currently modifying an existing PLL MathCAD model, and built a PLL hardware application. Final Team C deliverables include a Literature Search Report, interactive MathCAD Model, and a PLL hardware application presentation.

Books, articles and application notes were researched and a compilation of all information pertaining to areas of interest were summarized in a report and documented. Conclusions drawn from research regarding frequency step response of a PLL in the time domain, and integrator capacitor choices within the loop filter have been provided in the form of a written document titled PLL Literature Search.

An existing third order MathCAD PLL model will be expanded to incorporate up to a fourth order PLL model. MathCAD model revisions include step response plots of a PLL in the time domain as well as a simplified user environment. A simple, more robust MathCAD modeling tool will give Motorola customers greater flexibility in creating useful phase-locked loop applications. Customer input and output can be displayed at the beginning of the MathCAD model in a coherent manner.

Team C has built and will demonstrate a frequency multiplier circuit using a PLL. Motorola has provided Team C with the MC13175 evaluation kit, which includes the MC13175 PLL chip and related components necessary to build a PLL multiplier circuit. 

On April 24, 1998 Team C will present at a design conference at NAU's DuBois Center in the Meadows room starting at 9:00 A.M. Later that afternoon the Team will have a design booth set up for people to visit and see a demonstration of the hardware and software model portions of the project.

Last updated by Michelle East: April 22, 1998.